![]() Zen employs a branch fusion technique inside of the op cache so it can hold two ops in a single-op form. The op cache is a big advance, but the architects also devised a scheme to increase its density and magnify the performance gains. As expected, Clark declined to comment on the specific length of the pipeline but noted that the op cache scheme allows the company to shorten it. This technique boosts performance and saves power by reducing pipeline stages. Micro-ops are also stored in the op cache, which, in turn, serves frequently encountered ops to the queue. Data flows into decode, which then issues four instructions per cycle to the micro-op queue. It all begins with branch prediction, which feeds instructions into the 64K 4-way I-Cache. The high-level block diagram illustrates the flow through the core. Clark noted that his team worked hard to ensure that clock gating doesn’t affect the speed paths or critical areas of the chip. There is always a bit of a performance tradeoff associated with clock gating, and it can generate bugs as well, so striking the right balance is critical. AMD uses a multi-level clock gating strategy that reduces power consumption of subsections of the core when they aren’t busy. Accelerated performance speeds the “race to idle.” A higher IPC allows the CPU to satisfy workloads faster and thus shutter portions of the chip quickly. ![]() The 14nm FinFET provides more performance within a similar power envelope, and the performance boost is actually the key to reducing overall power consumption. The road to 14nm FinFET is well traveled the company began its FinFET journey with the Polaris GPUs. The first stop on the road to reduced power consumption consisted of discarding the 28nm process that AMD employed with the Excavator/Steamroller microarchitectures and adopting GlobalFoundries’ 14nm FinFET process. Let's take a closer look at what steps AMD's taken to regain its footing. However, the fact that a 40% increase only brings Zen to par, or possibly slightly above, the Core i7-6900K (sprinkle grains of salt, liberally), serves to illuminate just how far AMD is behind.Įveryone loves the underdog, but only if they win. Of course, a 40% IPC increase in one generation is much more impressive than Intel's comparatively unimpressive steady trickle of improvements over several generations. One could rationally assume that Intel's new process, architecture and optimize cadence gives it plenty of time to tweak its existing Skylake architecture into a more power-efficient Kaby Lake design, so the clock is ticking for AMD. For now, AMD has treated us to vague descriptions of a radical performance increase within the same power envelope as Excavator, but it has not released any hard data (such as TDP) to cement its claims. Intel has set the power efficiency bar very high, so the onus is on AMD to meet or exceed those expectations. In fact, Intel had just presented a run-through of its power optimizations on its aging Skylake architecture (Speed Shift and the like) on the same stage. The power-first thinking isn't entirely new the industry has been pounding the power drums for a decade. Clark stated that his goal was to "place power on equal footing with frequency and performance," which allowed his team to address power challenges at the early stages of the design process, instead of just trying to tweak a design with existing (and fundamental) inefficiencies. It's always easier to fix the wiring before you've hung the sheetrock, and AMD found a similar problem with its previous design flow. In the past, AMD instituted power refinements later in the design process, but unfortunately, the optimizations occurred after it had already laid the bulk of the architectural foundation. Defining a strict power consumption envelope only compounds the problem, so AMD shook up its design process and viewed every architectural decision, from its infancy, through the prism of power consumption. Designing a microarchitecture that can scale from low-powered fanless notebooks to the fastest supercomputers is fraught with challenges, but achieving a 40% boost in IPC at the same time is even more daunting.
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